Blocking and Non-Blocking Assignments Verilog -

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I always have code in block block (code 1) and non-blocking (code 2) assignments.

But why is the output different in both cases?

I know the queue for the event, but I probably can not understand that the "Always @ (CLK)" description will be placed in the queue. 

  Code 1 module OSS 2 (CLK, D); Output Clock; Reg clk; Input D; Initial start # 10 clerk = 0; $ Monitor ("% d% b", $ time, clk); Initial $ 100 end; Always @ (CLK) # 10 CLK = ~ CLK; Endmodule // Code generation 1 10 0 20 1 // Code 2 module OSS 2 (CLK, D); Output Clock; Reg clk; Input D; Initial start # 10 clerk = 0; $ Monitor ("% d% b", $ time, clk); Initial $ 100 end; Always @ (CLK) # 10 CLK & LT; = ~ Clk; Production of Endmodule / Code 2 2 10 0 20 1 30 0 (becomes 90) 90 0    
 
 
 For clarification purposes, I first resolved the contents of the two loops and opened the extended components for the break down. The code below will simulate.  
   always @ (clk) # 10 clk = ~ clk;    
  Initially (1) // To see the loop, functionally starts with 'always' as well as // procedural block starts Is: loop0_unraveled @ (clk); // continuity of the loop suspended until clk # 10 changes; // Loop continuation suspended 10 times units clk = ~ clk; / * Eval '~ clk' now * update clk now * / end start: loop1_unraveled start // this block is equivalent to functional '@ (clk)' reg smpl_clk; // local variable smpl_clk = clk; // Sample $ display ("% t :: pre-suspended: smpl_clk =% b clk =% b", $ time, smpl_clk, clk); Wait (CLK! = Smpl_clk); // Unless the continuation of the loop is suspended / * 1. Any blocking statements can not be executed, go to the next area. 2. All other areas are empty * 3. The remaining events are blocks * 4. Nothing Quit, Exit Simulation * / $ display ("% t :: Post-suspended: smpl_clk =% b clk =% b", $ time, smpl_clk, clk); End # 10; // accessible clk = ~ clk; End   
   always @ (clk) # 10 clk & lt; = ~ Clk;    
  To begin loop (1) // loop, functional 'start' starts simultaneously as well as // procedural block starts : Loop0_unraveled @ (clk); // continuity of the loop suspended until clk # 10 changes; // Suspend the continuation of the Loop 10 times the units CLK and LT; = ~ Clk; / * Eval '~ clk' now, * after all blocking statements * Update clk has been suspended * / end start: loop1_unraveled start // This block is functional '@ (clk)' reg is equal to smpl_clk; // local variable smpl_clk = clk; // Sample $ display ("% t :: pre-suspended: smpl_clk =% b clk =% b", $ time, smpl_clk, clk); Wait (CLK! = Smpl_clk); // True / Unless the continuation of the loop is suspended / * 1. Any blocked statements can not be executed, go to the next area * 2. Update the NBA area * 3 Go back to the active area * 4. Actual truth, continue * / $ display ("% T :: post-suspended: smpl_clk =% b clk =% b", $ time, smpl_clk, clk); End # 10; // Access CLK and LT; = ~ Clk; End of end // Go to the top of the loop   
 As I have already mentioned, the work that triggers itself in practice is not very common Clock generator usually has some implanted like this Occurs:  
  Initial start # 10 clk = 0; Forever # 10 clk = ~ clk; End   
 or  
  always # 10 clk = (clk === 1'b0);

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